1. Field of Invention
This invention relates generally to silicon-on-insulator (SOI) CMOS devices and specifically to processes for forming SOI devices having a low resistance.
2. Description of Related Art
Silicon-on-insulator (SOI) devices are those which are formed in a thin silicon layer which overlies an insulating layer. The insulating layer, in turn, overlies a second silicon layer. Fabricating integrated circuit (IC) devices in a thin silicon-on-insulator (SOI) layer, as opposed to fabricating such devices in a much thicker bulk silicon structure, allows for lower parasitic capacitance and for greater channel currents which, in turn, allows for faster speeds. The lower parasitic capacitance also allow for reduced substrate crosstalk and, thus, for reduced noise. In order to fully realize these advantages, the SOI layer within which IC devices are fabricated should be less than approximately 1000 .ANG. so that the source and drain regions of these IC devices are proximate to the underlying insulating layer. Further, the source and drain regions of devices formed within an SOI layer should be shallow in order to minimize short channel effects.
Unfortunately, devices fabricated in a thin SOI layer and having relatively shallow source and drain regions typically exhibit an unacceptably high series resistance between the source and drain regions. This high series resistance results in slower speeds and therefore may abrogate the superior speeds sought when using SOI technologies. Accordingly, there exists a need to reduce the series resistance of such SOI devices without compromising the superior short channel effects realized by a shallow source and drain.
It is known that the series resistance of a transistor can be decreased by forming a layer of silicide within the source and drain of the transistor. The silicide material may be, for instance, Titanium Silicide (TiSi.sub.2) or Cobalt Silicide (CoSi.sub.2). A layer of silicide is conventionally formed by first depositing a thin film of titanium over the surface of the transistor. The transistor is then thermally annealed in a nitrogen ambient at a temperature between approximately 400-700 degrees Celsius for approximately 10-200 seconds. This thermal annealing induces reactions between the deposited titanium and the underlying silicon in, for instance, the source and drain of the transistor, to form titanium silicide (TiSi.sub.x). The deposited titanium does not react with insulating materials such as, for instance, oxide or nitride layers. Thus, portions of the titanium layer overlying insulating materials in, for instance, a sidewall spacer laterally surrounding the gate of the transistor, remain in a metallic titanium state. Further, titanium proximate to a top surface of the resulting titanium silicide layer, as well as titanium proximate to a top surface of remaining portions of the deposited titanium layer, react with the ambient nitrogen to form a thin layer of titanium nitride (TiN). This layer of titanium nitride, as well as the remaining portions of the deposited titanium layer, are removed during a subsequent etching step, thereby leaving intact the titanium silicide layer within, for instance, the source and drain of the transistor. A second thermal annealing step is performed at a temperature of between 600-900 degrees Celsius for approximately between 10-200 seconds to convert the titanium silicide into a stoichiometric composition. For instance, where the titanium silicide is in the form TiSi.sub.2, the second annealing converts the TiSi.sub.2 from a C.sub.49 phase to a more conductive C.sub.54 phase. The resulting layer of titanium silicide increases the conductivity of the source and drain regions and, thus, allows for a lower series resistance.
Forming a layer of silicide in the manner described above is, however, problematic when formed within selected regions of a semiconductor device fabricated on a thin underlying layer of silicon such as, for instance, an SOI layer. Where the underlying silicon layer is less than approximately 1000 .ANG., the titanium undesirably agglomerates during the thermally induced reactions which form titanium silicide, thereby resulting in a non-uniform concentration of titanium in the layer of titanium silicide. In addition, undesirable voids may be formed within silicon portions underlying the titanium silicide layer. As a result, the conductivity of the resultant titanium silicide layer is undesirably reduced which, in turn, increases the series resistance of the semiconductor device. Further, non-uniformities within the resultant titanium silicide layer may degrade the performance and reliability of the target transistor. Accordingly, it would be desirable to minimize the agglomeration of titanium during formation of a titanium silicide layer within, for instance, the source and drain of a transistor formed in a thin layer of silicon.